1. Technical Field
The invention relates generally to integrated circuits, and more particularly relates to a digital phase lock loop clock generator including clock multiplication.
In an exemplary embodiment, the clock generator provides internal clock generation for a single chip memory and bus controller used in a computer system based on an x86 microprocessor architecture, generating (a) a 1.times. (66 MHz) clock for interfacing to the microprocessor local (system) bus, and (b) 1/2.times. (33 MHz) or 2/3.times. (40 MHz) clock for interfacing to a VL peripheral bus.
2. Related Art
Clock generation and distribution schemes for large scale integrated circuits commonly use phase locked loops (PLLs) to synchronize to an input reference clock. Synchronization is obtained by phase locking the generated output clock to the input reference clock (using feedback of the output clock), where the output clock is generated using either of two design approaches: (a) analog using a voltage controlled oscillator, or (b) digital using a digital skew compensator.
Without limiting the scope of the invention, this background information is provided in the context of a specific problem to which the invention has application: providing an improved digital clock generator that (a) performs skew compensation with accurate control over duty cycle, (b) achieves phase locking with minimized jitter, and (c) performs clock multiplication with accurate control over output clock edge generation.
PLLs using voltage controlled oscillators (VCOs) are sensitive to electrical noise on the chip and on ground/voltage reference points. As integrated circuit speeds increase, designing a stable VCO becomes problematic, particularly in view of process variations during chip fabrication, such that the PLL can be a significant contributor to yield loss. Moreover, VCOs typically require a long lock delay between the time the reference clock is present and the time the PLL clock is fully in lock (synchronized) with minimum skew and a stable frequency.
Digital PLL designs have been able to overcome many of the disadvantages of PLLs based on VCOs. In the typical digital PLL design, phase locking is achieved using phase detection to detect alignment (or misalignment) of the generated and reference clocks, and a skew compensation to introduce an appropriate amount of delay through the clock generator to compensate for input reference clock delay through the input pads, clock trees, etc.
Skew compensators typically use a digital delay line with a tapped inverter chain--the output tap is adjusted to introduce a selected amount of delay. The phase detector is used to provide an up/down delay selection signal to the skew compensator--the delay selection signal indicates whether the output delay should be increased or decreased (i.e., adjusted up or down )to achieve phase locking. One problem with current digital PLL designs is minimizing any change in duty cycle introduced by skew compensation--the tapped inverter chains used in the skew compensators can alter duty cycle because rising and falling clock edges may propagate through the inverters with different transition times. Another problem is jitter in the generated output clock introduced by phase detection--as the phase detector attempts to achieve phase locking, small changes in the alignment of the reference and feedback (generated) clocks can result in over-compensating up/down adjustments that translates into jitter in the generated clock.
Systems often include clock generators with multiplication logic to provide internal generated clocks that are some multiple of the input reference clock. For example, in the case of a memory and bus controller, interface to a microprocessor may be at 1.times. the system clock (e.g., 66 mhz), but interface to a peripheral bus (such as a 33 or 40 MHz VL-bus) may be at 1/2.times. or 2/3.times.--the 2/3.times. fractional multiplication would be provided by a 2.times. multiply and a divide-by-three.
Current clock multiplication schemes commonly employ analog components to accurately generate a predetermined number of clock edges each clock period from the leading edge of an input clock (i.e., the PLL generated clock)--these clock edges are combined in an output waveform generator to provide an appropriately multiplied clock (i.e., for 2.times. multiplication, four clock edges are generated). Fully digital schemes using delay lines are available--the leading edge of the input clock is fed back with an appropriate delay a predetermined number of times to generate a corresponding number of edges.
Because even digital PLLs are sensitive to process variations that result in operational variations, systems using clock generation commonly include process variation detection structures. One common approach is to provide a digital delay line with a tapped inverter chain in which the inverters are process sensitive (i.e., including combinations of process layers such as metal 1, metal 2, poly)--the delay through the inverter chain is then a measure of process variation. These delay line structures, because they are by design process sensitive, are typically not used for any function other than process variation measurement.